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https://doi.org/10.1007/978-981-16-1056-1_58
Copy DOIPublication Date: Jan 1, 2021 |
Citations: 2 |
This paper aims to increase the speed of solving waveform simulation problems with further reduction in area of design structure. Multiplier, adder and delay unit are the main blocks for the implementation of the FIR filter. In several processors, multiplication plays a key role for arithmetic operations. In this paper, the ripple carry adder is considered as an adder block in Vedic multiplier and carry look ahead adder as an adder block in shift add multiplier, for the partial products addition. The proposed design of Vedic multiplier uses the technique of Vedic mathematics to improve the performance. The delay and area for different data sizes are computed and simulation graphs are presented. The results show that, with the help of above design structure, considerable amount of reduction is experienced in delay and area of the filter along with minimised power consumption using Xilinx ISE 14.7. The proposed FIR filter structure using shift add multiplier with carry look ahead adder reduces the area and obtains the results in a short time.
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