An optimized architecture for IEC 61850 process bus

Abstract

The IEC 61850-9-2 standard [1] focuses on transparency and standardization of data communications. Implementation issues such as suitable architectures, reliability, time synchronization, data sharing, maintainability, testability, and scalability remain outside the scope of the standard. Process bus architecture is a missing element on the road to implementing the next generation of Protection and Control (P&C) systems. In this paper, architecture refers to the definition and structure of the process interface points, partitioning and allocation of functions to the devices, the underlying structure of time synchronization, settings and firmware management, failure-tolerant communication framework, required data throughputs and latency considerations, data traffic patterns, and other related aspects. Careful analysis of the rules and symmetries occurring in topologies of high voltage substations allow for identification of process bus data traffic patterns, origins, destinations, and throughput required to accomplish a simple, robust, scalable and flexible IEC 61850 process bus architecture. The primary equipment itself drives a logical and natural architecture for a communication-based protection and control scheme. This paper presents a practical process bus architecture conforming to IEC 61850-9-2 that fits the task of protection and control of substations by drawing from the universal topology rules of substations.