An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

Abstract

In this paper, the impact of negative bias temperature instability (NBTI) on dynamic logic circuits is analyzed and a design technique for a wide fan-in domino gate based on Genetic Algorithm (GA) optimization is proposed. In this technique, the degraded delay due to NBTI during the lifetime of the circuit is minimized subject to the constraints on area, power consumption and unity noise gain (UNG). The proposed optimization method is implemented in a 65-nm technology for a lifetime of 3 years. In comparison with a typical design, the optimized results show an improvement of more than 21.6% in delay during the circuit lifetime with a negligible change in the power and the UNG. The proposed method has the advantage that it can be used for any desired circuit lifetime with any reasonable constraints on design parameters, just with setting the corresponding parameters in the algorithm.