An optimised multi value logic cell design with new architecture of many value logic gates

Abstract

Propose thesis work is a design of a Multi Logic Memory cell of four logic levels which can hold Logic 0, Logic 1, Logic 2 & Logic 3 and also propose an Interface module design between multi logic system with binary systems, thesis work can reduce the no. of wires required to parallel interface with normal memory and also can increase the speed of simple serial data transfer.