Abstract
An O(1) time algorithm to multiply two K-bit binary numbers using an N/spl times/N bit-model of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in AT/sup 2/ optimality over 1/spl les/t/spl les//spl radic/N in a variant of the bit-model of VLSI.
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