Abstract
This letter reports the demonstration of 1.2 kV 4H-SiC Schottky-integrated MOSFETs (JBSFETs) achieving the same specific on-resistance as the pure MOSFET by using an innovative layout approach as well as novel deep P-well structure. The proposed JBSFET significantly reduces the specific on-resistance accomplishing 2x reduction in the chip size, when compared with the traditional, chip-to-chip parallel connection of separate MOSFET and JBS diode. Moreover, the leakage current originated from the Schottky contact was successfully suppressed by adopting a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.8~\mu \text{m}$ </tex-math></inline-formula> deep P-well structure implemented by channeling implantation. Device design strategy with layout approach, fabrication, and static and short-circuit characteristics are discussed in this letter. In order to understand and clarify the experimental results, 2D simulations were conducted.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
