Abstract
Barrier synchronization is a useful parallel programming construct for ensuring that all processors are at a particular location in the code before any processor is allowed to continue. Barrier synchronization is integral to programming models such as the Bulk Synchronous Parallel model. Specialized hardware is often used to improve the performance of a barrier synchronization operation. With continued improvement in processor performance, more efficient synchronization mechanisms are required to counter the rising relative cost of synchronization operations. A high-speed, distributed barrier synchronization mechanism has been developed for broadcast-based optical interconnection networks. This mechanism avoids multiple conversions between optical and electrical signals by having each processor locally decide whether the barrier in which it is participating has been satisfied. It also allows arbitrary sized partitions to be built dynamically during the execution of a program. Simulations of the current hardware design estimate that the barrier synchronization requires less than 300 ns for a 128-processor system.
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