An OPC approach to improve logic gate features corner fidelity

Abstract

For deep sub-wavelength lithography, loss of wafer fidelity, such as line end shortening and corner rounding, is a known patterning phenomenon due to the diffraction limitation of the optical systems and some other processing effects. Without properly correcting these effects, particularly for gate corner rounding at the active area, sometime device performance might be limited or wafer yield will be impacted. It is addressable to improve the feature fidelity by OPC (Optical proximity correction) methodology, which is intentionally to offset the light distortion while in mask synthesis process. However, it is most likely becoming better, but not be completely solved at all. In this paper, first, the acceptable gate corner rounding criteria is examined. From the design rule constraint for gate region and test key electrical performance result, primary geometrical specification is determined. At the same time, considering inline process variation, such as ADI CD/overlay variation and loading effect of etching process, then the OPC corner rounding target specification comes accordingly. Second, OPC countermeasure for gate corner rounding improvement is studied. Usually gate CD uniformity is increased near the corner region, that is, gate poly CD is larger than expectation at the beginning of the active area near the L-shape or U-shape poly pattern. Since the transistor performance will be degraded, the improvement for corner rounding is important for OPC development. Aggressive OPC recipe to manipulate the polygon is required. We make use of localized fragmentation rule as well as specific retargeting to eliminate the impact of corner rounding effect in optical system. This methodology for corner fidelity improvement was proved by the wafer result.