An on-chip continuous time power supply noise monitoring technique

Abstract

A continuous-time power supply noise monitoring technique features a coverage of voltage domains at Vdd as well as at Vss and multi-channel probing at more than a hundred locations on power planes in a circuit. Methods toward quality on-chip power supply noise measurements are derived. A calibration flow eliminates the offset as well as gain errors among probing channels. A combined evaluation of on-chip measurements and off-chip circuit simulation precisely characterizes probing performance. In addition, consistency was ensured among noise waveforms captured by sampled-time precise digitization and by the proposed continuous-time monitoring. A 90-nm CMOS on-chip monitor prototype demonstrates dynamic power supply noise measurements with ± 200 mV at 1.2 and 0.0 V, respectively, with less than 3 mV offset voltages among 240 probing channels, and with the effective bandwidth of 1.0 GHz.