An on‐line error‐detectable high‐speed array divider

Abstract

AbstractThis paper proposes an on‐line error‐detectable high‐speed array divider. The divider is based on the high‐speed division algorithm using the redundant binary representation. It can execute an n‐bit division in a computation time proportional to n, has a regular cellular array structure suited to LSI implementation, with the hardware complexity proportional to n2, and a feature that any error caused by a single cell fault can be detected during the normal operation. By utilizing the locality of the computation in the divider, the on‐line error detection is realized based on the check by the residue code for the dividend, divisor, quotient and the remainder, as well as some other additional checks.