An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design

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In complex system design, it is often desirable to start the system specification at higher levels of abstractions, e.g. at the algorithmic level. The necessary refinements are then produced by commercial or academic high-level synthesis systems. More and more often, the integration of user-defined RT components in the algorithmic specification plays an important role. First, some functional and timing behavior can only be implemented at the RT level, e.g. interrupt handling, and interface components. Second, several RT components may already exist and are appropriate for reuse. Third, the re-implementation of VHDL models emulating this behavior at the algorithmic level is expensive and time-consuming. Finally, several synthesis, simulation, and test environments exist which can be used for descriptions at different abstraction levels. Therefore, this paper addresses the problem of mixed abstraction level specifications for simulation and behavioral synthesis using object oriented component models. For this, the VHDL standard [IEEE93] without any extensions is used and the usual simulation and synthesis systems can be applied. The communication between algorithmic descriptions and VHDL components at the same or at lower levels is executed using VHDL procedures. To reduce the design time required for the insertion of these procedures in the algorithmic specification, a preprocessor has been developed. The preprocessor allows the procedures to be applied without any extensive declarations of the corresponding RT components. The implementation of procedures emulating the component behavior at the algorithmic level is also possible.