Abstract
A new type of dynamic RAMs, an N-well CMOS dynamic RAM, is proposed as a promising candidate for future VLSI RAMs and experimental results of a 4-kbit RAM, fabricated with an advanced 2 µm lithography are presented. For the design of greater than 256-kbit dynamic RAMs, two major problems should be solved: an increase of a substrate current and an α-particle induced soft error problem. The N-well CMOS RAM technology will be one solution to overcome these problems. The use of PMOS transistors as load elements in peripheral circuits of the N-well CMOS RAM reduces the substrate current by at least two orders of magnitude and the potential barrier between the N-type well and the P-type substrate rejects holes generated in the substrate, resulting in the reduction of soft error rates.
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