Abstract
We consider basic algorithms and processing technologies for integrated circuit layout images. The images represented as a set of frames can regard as a dataflow and the processing are perfectly suited for parallel implementation. We propose a framework architecture for designing parallel systems of image dataflow processing. The framework uses the algorithm of a virtual associative network for increasing processing speed and system throughput during runtime.
Highlights
The modern semiconductor manufacturing needs to control all of the critical process modules that drive integrated circuit (IC) manufacturing success
In this table we show the relative values, that characterize the improvement of processing time for virtual network (VN) algorithm
This schema was compared with dynamic processing schema, which was controlled by VN algorithm
Summary
The modern semiconductor manufacturing needs to control all of the critical process modules that drive IC manufacturing success. Layout image is represented as a set of raster frames and consists from areas, the boundaries of which are rectangle, polygon, circle or ellipse. A problem of design of parallel processing systems can be solved by use of design automation tools at various development stages. This approach is good applicable to deterministic dataflow processing task, because of its comprehensive definition. For automation of processing of stochastic image flows the developer can use the technique of load balancing This technique is based on decomposition of algorithm on separate modules, them solves the part of the problem. The ability of online schedule optimization allows applications to achieve high speed and utilization of parallel processing system
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