An LDE-Aware g m /I D -Based Hybrid Sizing Method for Analog Integrated Circuits

Abstract

Layout-dependent effects (LDEs) have become increasingly more important in the synthesis of analog integrated circuits. In this article, a two-phase hybrid sizing method for high-performance analog circuits is proposed. It consists of g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> -based device characterization, circuit modeling, sensitivity-based constraints for LDEs, mixed-integer nonlinear programming (MINLP) in the first phase, and many-objective evolutionary algorithm (many-OEA)-based sizing in the second phase. In the first phase, accurate device characterization is handled with little modeling effort thanks to the g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> design methodology. Then, the LDE parameters that are linked to the normalized dc current are further optimized with the aid of sensitivity analysis. Thus, a variety of electrical, geometrical, and LDE-related constraints can be conveniently integrated into modeling of the sizing problem. In the second phase, the many-OEA-based sizing refiner can further optimize the LDE parameters by using more detailed layout information via our proposed model. A new floorplan variation scheme is also applied to improve computation efficiency and enhance optimization effectiveness. The experimental results demonstrate high efficacy of our proposed methodology in LDE-aware analog sizing optimization.