Abstract
This paper presents a two stage L-band power amplifier realized with a 0.32 ㎛ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 ㏈ small-signal gain and 15.7 ㏈m output 1-㏈ compression power at 1.9 ㎓ with a 122 ㎃ DC current from a 4 V supply. The amplifier delivers a 19.7 ㏈m. This paper presents a two stage L-band power amplifier realized with a 0.32 ㎛ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 ㏈ small-signal gain and 15.7 ㏈m output 1-㏈ compression power at 1.9 ㎓ with a 122 ㎃ DC current from a 4 V supply. The amplifier delivers a 19.7 ㏈m saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 ㏈m saturated output power with a 20.4 % maximum PAE. The die area is 1.9 ㎜ x 0.6 ㎜.
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