Abstract
The paper presents a computer program 'VHDLMultGenerator', which is an IP core generator supporting synthesis of arithmetic multiplication. On the basis of some simple options selected by the user the program generates a synthesizable VHDL code of a multiplication block which can be incorporated in a bigger design. The VHDL code uses a mixed dataflow and structural description style at the RTL level of abstraction. The code is in general architecture-independent and can be ported to any PLD synthesis software which supports VHDL design entry. Several algorithms of performing multiplication, implemented in the IP core generator, are also briefly described.
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