An Investigation into the Package and Printed Circuit Board Assembly Solutions of an Ultrathin Coreless Flip-Chip Substrate

Abstract

Flip-chip technology has been widely accepted as a solution for electronic packaging of high-pin-count devices. Due to the demand for smaller and thinner package dimensions, coreless build-up substrates will be used in industry to carry the die by solder bumps due to the advantages of shorter transmission route and lower inductance and thermal resistance. However, coefficient of thermal expansion (CTE) mismatch between the Cu trace and the laminate often causes the coreless substrate to warp, which leads to failures such as nonwetted solder bumps and interfacial cracking during assembly and reliability tests. In a previous study, assembly of a six-layer polyimide-based coreless flip-chip package was achieved by a 17 mm × 17 mm die with 4355 Sn-37Pb solder bumps, an amide-based underfill, and 1521 Sn-3.0Ag-0.5Cu solder balls. For determination of its board-level reliability characteristics, the component was mounted on a printed circuit board (PCB) using a conventional surface mount technology, and 10 test vehicles were assembled for assessment of their reliability under a temperature cycling environment. The experimental results show that the characteristic life of the PCB assembly exceeded 1500 cycles and that failure resulted from fracture of the outermost solder balls on the substrate side. This was different from the failure mode of die cracking when the package experienced hundreds of temperature cycles at the component level because the rigid PCB, through solder balls, moderated the deformation of the coreless flip-chip package. Hence, the concentrated bending stress at the die edge region was lowered. Finally, the local CTE mismatch between the stiffener and the PCB dominated the fatigue fracture of the outermost solder balls to become the main failure mode.