An Interconnect Sheet Resistance Model Considering CMP Pattern Effects in 45nm Process

Abstract

Abstract Side effects in Cu interconnect chemical mechanical polishing (CMP) process - dishing and erosion - will both influence chip surface topography and deteriorate interconnect electrical characteristics such as interconnect resistance. In this paper, test chip was designed for measurement of both surface topography and electrical characteristics of Cu interconnect after CMP process. An interconnect sheet resistance model considering dishing and erosion effects is proposed and verified by experimental results. For most test structures, difference between prediction results and measurement results are less than 4%. This model is applicable to other CMP processes in which dishing and erosion are positive or negative, and it can also be easily integrated into state-of-art CMP simulators for accurate interconnect resistance prediction.