An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs

Abstract

State-of-the-art FPGA design has become a very complex process primarily due to the aggressive timing requirements of the designs. Designers spend significant amount of time and effort trying to close the timing on their latest designs. In that timing closure methodology, Physical Synthesis plays a key role to boost the design performance. In traditional approaches, user performs placement followed by physical synthesis. As the design complexity increases, physical synthesis cannot perform all the optimization steps due to the physical constraints imposed by the placement operation.In this work, we propose an interactive methodology to perform physical synthesis in the pre-placement stage of the FPGA timing closure flow. The approach will work in two iterations of the design flow. In the first iteration, the designer will perform the regular post-placement physical synthesis operation on the design. That phase will automatically write a replayable-file which will contain information about all the optimization actions. That file also contains all the attempted optimization moves what physical synthesis deemed beneficial from QoR perspective, but was not able to accept due to the physical constraint. In the second iteration of the design flow, the designer will perform all those physical synthesis optimizations by importing the replayable file in the pre-placement stage. In addition to performing the physical synthesis flow's changes, it also performs the optimizations that were not possible in the traditional physical synthesis flow. After these changes are made in the logical stage of the design flow, the crucial placement step can adapt to the optimized/better netlist structure. As a result, this approach will greatly help the users reach their challenging timing closure goal.We have evaluated the effectiveness and performance of our proposed approach on a large set of industrial designs. All these designs were targeted towards the latest Xilinx Ultrascale™ devices. Our experimental data indicates that the proposed approach improves the design performance by 4% to 5%, on an average.