An interactive layout design system with real-time logical verification and extraction of layout parasitics

Abstract

The interactive layout design system PARIS (placement and routing interactive system), which meets the special requirements of cell-based design methods, like gate array, bipolar analog standard cell, and transistor array approaches, is discussed. A real-time logic connectivity extraction tool is provided, which is integrated into the system's interactive layout editor GRILLE. Apart from online execution of formal layout checks during the design process, the system enables online net-list extraction of arbitrary layout parts and extraction of specific parasitics for bipolar transistor array applications. All PARIS tools for these real-time logic connectivity verification and parasitics extraction facilities support a hierarchical design philosophy based on a detailed functional and logical description of the layout components. This yields significantly shorter design cycles and avoidance of time-consuming net-list comparisons on the transistor level, which are superfluous especially for cell-based design methods. >