An interactive and dynamic scratchpad memory management strategy for multi-core processors

Abstract

An interactive and dynamic Scratchpad memory (Scratchpad) management approach is proposed in this research manuscript to target multi-core processors. By using MMU an integrated (memory management unit), it can be useful for an existing embedded system that maps into a virtual space the physically addressed Scratchpad memory. A hardware Unit MRSU (Memory Reference Sampling Unit) is introduced depend on mass-count disparity, with a very low probability that models the memory reference data stream. One of the memory addresses is considered as a captured address that is present in a repeatedly referenced memory segment. MRSU generated a hardware interference and the captured / identified repeatedly accessed memory block is placed, through the software, into the Scratchpad space. The page table is also modified by the software so that the Scratchpad memory data block will be forwarded by the follow-up memory accesses. In multi-core processor for Scratchpad management, this proposed strategy is specifically adequate without depending on profiling information and compiler. By profiling or static analysis, the memory accesses behaviour cannot be guessed and a RTOS (Real-Time Operating System) is mostly presented in such an environment. By executing numerous operations on a small Real-Time Operating System the proposed Scratchpad allocation strategy is evaluated with preemptive scheduling. In contrast with a referenced cache-only system with just 1% performance degradation at runtime, in terms of energy consumption on average, this proposed method can achieve an 11% reduction which can be observed in experimental results.