An inter-scale simulation method for TSV 3D IC based on linear superposition algorithm and TSV model sharing strategy

Abstract

TSV Three-Dimensional Integrated Chips (TSV 3D ICs) contains extremely large number of irregularly distributed TSVs. As the decreases of size and pitch, the interaction among TSVs and substrate becomes significant. However, the existing fine mesh simulations for small number of TSVs rarely consider the global influence, the current multiscale simulations for package or wafer cannot assess all TSVs' structural state quickly. Therefore, the inter-scale simulation method considering the interactions between small-scale and large-scale simulations is proposed. The model sharing strategy decomposes the finite element analysis (FEA) simulation into a series of linear superposition algorithm (LSA) simulations, making it possible to obtain the detailed structural response of all TSVs concerning the global influence quickly. In addition, the equivalent properties of large yield TSVs are recalculated and fed back to the global simulation to reconstruct a more accurate global model for iterative simulation. The single TSV fine mesh simulations validate the reliability of the established LSA simulator. The TSV chip simulation under single point bending load shows that the relative error of stress is less than 0.0125 % of the global simulation, and it is 1.63 % of the fine mesh simulations, Meanwhile, the solution time is reduced to 2.2 % of the FEA method, and the memory consumption is only 0.088 %.