An instruction fetch unit applicable to 32-bit and 16-bit instruction sets together

Abstract

In microprocessors, instruction fetch (IF) unit is a very critical part to gain high performance. In our design of a 32-bit RISC microprocessor core, we devise two instruction sets (32-bit and 16-bit) for both high performance and code density. The IF unit uses the same structure to get either 32-bit or 16-bit instruction from memory, so it almost don't increase the area cost. Moreover, when 32-bit instruction register is used for 16-bit instruction fetch, the remainder 16-bit instruction register acts as an instruction buffer, thus IF unit can feed instruction decode (ID) unit with one instruction per clock under most circumstances, even when memory delay occurs. This IF unit is also designed as a highly independent module with simple interface, and it is easy to reuse in other designs. To expedite instruction fetch speed, we use a separate branch address calculation adder, so we can get the destination address in the same cycle with the branch instruction is decoded. From synthesis and simulation results, the IF unit shows high efficiency.