An instruction fetch policy handling L2 cache misses in SMT processors

Abstract

In simultaneous multithreading (SMT) processors, co-scheduled threads share the processor's resources, but at the same time compete for them. A thread missing in L2 cache may occupy most of available resources for a long time, causing other threads to run slower than they could or even stall because of lack of resources. As a result, the overall performance of SMT processors is degraded. In this paper, we propose a novel fetch policy called MFP (multiple fetch priorities) to prevent the negative effects caused by L2 cache misses. In our policy, there are three fetch priority levels for each thread and threads are assigned different fetch priority based on their cache behaviors. Each cycle, MFP fetches instructions from the threads with the highest priority. Results show that our policy outperforms previously proposed fetch policies for all types of workloads, especially for memory bounded workloads, whether using IPC as a metric or using the harmonic mean as a metric. Results also tell that our policy shows different degrees of improvement over other fetch policies. The increment over PDG is greatest, reaching 19.2% in throughput and 27.7% in Hmean on average