AN INNOVATIVE IMPLEMENTATION OF ENCRYPTION ALGORITHM ON FPGA IN MANY CORE ARCHITECTURES.

Abstract

In this paper, we grant the remodeling with the aid of “categorizes” of amenities—a category being explained as a group of amenities that share innovative operations and are mapped to the same key value based on Encryption schemes of sub-bytes transformation method. The sub-bytes transformation method is the high-speed standard Encryption module. AES Algorithm is synthesized by utilizing Verilog code and encountered into FPGA. We implement a new design of AES Algorithm in FPGA in many core Architectures which is an in-built one.