An industrial CMOS process family adapted for the fabrication of smart silicon sensors

Abstract

We present an industrial CMOS process family adapted for the fabrication of integrated microsensors by anisotropic etching of silicon with an electrochemical etch-stop (ECE). The modified CMOS processes provide wafers prepared with (a) a conducting network for the distribution of the electrochemical potentials and (b) a contact field to apply the potentials from a potentiostate to the wafer. Furthermore, the deposition of a PECVD silicon nitride masking layer on the planarized wafer back was implemented as extended back-end of the CMOS processes. The network and the contact field are created by a number of additional standard photolithographic steps performed on wafer steppers along with the photolithography of the standard metallizations. Therefore, the method can be applied to IC device technologies regardless of the minimum feature size or the wafer diameter. Up to now, the adaptation for microsensor fabrication has been implemented into 2- and 0.8 μm CMOS device technologies. Silicon wafers with reduced concentration of interstitial oxygen are used as standard starting material to improve the quality of the micromachined structures. A variety of microfabricated devices with co-integrated electronics such as ultrasonic transmitters and receivers for proximity sensing, integrated force sensors for atomic force microscopes (AFM), and smart chemical sensors for the detection of volatile organics are presented as applications and examples.