An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

Sang-Yeop Lee,Shuhei Amakawa,Hiroyuki Ito,Noboru Ishihara,Kazuya Masu

doi:10.1155/2013/584341

Sang-Yeop Lee, Shuhei Amakawa + Show 3 more

Open Access

https://doi.org/10.1155/2013/584341

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Abstract

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).

Highlights

Conventional multistandard wireless mobile terminals contain multiple RFICs
It is very difficult to reduce the scale of RF/analog circuit blocks, especially power amplifiers and oscillator circuits, including voltagecontrolled oscillators (VCOs) and phase-locked loops (PLLs), because of the presence of inductors that do not scale with advancements in technology
An inductorless PLL architecture, using the combination of a phase-locked loop, and injection locking with a ring VCO was proposed

Summary

Introduction

Conventional multistandard wireless mobile terminals contain multiple RFICs. To reduce production costs, one-chip wideband RF LSI systems are desired. In designing VCOs which generate signals in RF systems, ring-type VCOs (ring VCOs) are more attractive than LCresonant-type VCOs (LC VCOs) in terms of their small area and wide frequency tuning range since they do not use large passive devices. They have poor phase noise with relatively high power consumption. Cascaded PLL (CPLL) that can achieve injection locking at high frequencies from low-frequency reference is presented Detailed circuit designs, such as a VCO and a charge pump which are able to realize wide-band operation, and the measurement results obtained from an implementation in 90 nm CMOS process are presented in Sections 3 and 4, respectively.

Injection Locking in Frequency Synthesizers

Proposed Injection-Locked PLL Topology

Measurement Results

Conclusion