An Inductive Assertion Method for Register Transfer Level Design Verification

Abstract

This paper extends Floyd's inductive assertion method to formal verification of register transfer level (RTL) hardware descriptions. An RTL description with imbedded assertions about machine state will be the input to the verifier. The formal semantics of an RTL language for synchronous designs are defined, to make mechanical generation of verification conditions (VC's) possible. These VC's are to be fed to a theorem prover. Proof of all the VC's constitutes complete verification. The semantic rules define how time advances, in addition to how machine variables change. These rules make possible verification of real-time performance as well as logical correctness. Such real-time performance verification is important for some hardware designs. The paper also emphasizes the differences between software and hardware verification. An example is given to illustrate the formal verification method.