An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

Jaewon Park,Sungho Kang,Ki Chul Chun,Jae Hoon Lee,Kyomin Sohn,Sang-Kil Park

doi:10.1109/access.2021.3061349

Abstract

As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased. As a result, DRAM vendors perform post package inspections to provide fault-free DRAMs to the end customers. However, post package inspections require considerable test costs. To overcome this issue, an in-DRAM built-in self-test (BIST) mechanism is implemented in this study as an alternative solution. Herein, we propose compact and high test-coverage features for the in-DRAM BIST that to resolve the area problem when applied to a commodity DRAM. The proposed BIST secures the same test coverage with a shorter time than the conventional BIST. The proposed BIST reduces the test time by 52% of the DDR BIST in functions with the same test coverages. Further, the implemented BIST can achieved an area overhead of 0.051% based on a 16Gb DDR4 DRAM in the second generation of the 10-nm-class DRAM process.

Highlights

Dynamic random-access memory (DRAM) suppliers are mainly fabricating products using the 10-nm-class process
The retention test is used to check the gate-induced drain leakage (GIDL) component of the cell itself, but the repetitive test is used to check the effects of the variable retention time (VRT) due to noise generated during dynamic random-access memory (DRAM) operation; failures that do not occur in the retention pattern can be detected
The proposed built-in self-test (BIST) is mounted on a DDR4 16 Gb to determine the overhead, test time, and test coverage

Summary

Introduction

Dynamic random-access memory (DRAM) suppliers are mainly fabricating products using the 10-nm-class process. To minimize the size overhead and test time, the proposed BIST is configured with retention times that can be changed in fixed patterns. The test engine block creates the test patterns of the proposed BIST; VRT changes can be detected by applying the modified march pattern, and the proposed BIST creates a signal for the PBT mode controller to reduce the test time.

Results

Conclusion