An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters

Abstract

This paper presents an incomplete settling design technique for switched-capacitor pipelined analog-to-digital converters (ADCs) to improve conversion rate. An improved multiplying digital-to-analog converter (MDAC) is introduced to eliminate the memory effect between adjacent samples in the conventional MDAC with insufficient settling time. The repeatable interstage gain error and nonlinearity due to incomplete settling are then corrected by a digital background calibration scheme. Behavioral simulations of two 13-bit incomplete settling ADCs, one with the improved MDACs and the other with the conventional MDACs, are performed in MATLAB to verify the proposed technique. The simulation results show that, the first ADC has an almost undegraded dynamic performance until the settling time decreases to 30% of the complete settling time, and at the point of 30% complete settling time, the improvement of SNDR and SFDR over the second one is 36.2dB and 52.4dBc, respectively.