Abstract
In this paper, an analytical model has been developed for improved assessment of Miller capacitors for high-frequency metal?semiconductor field-effect transistors. Depletion layer underneath the Schottky barrier gate has been divided into four distinct regions, and by evaluating the charges associated with each region, gate-to-source ($C_{GS}$) and gate-to-drain ($C_{GD}$) capacitors, {commonly known as Miller capacitors,} have been defined accordingly. Mathematical expressions have been developed both for the linear as well as for the saturation region. Miller capacitors and their variation as a function of applied bias have been assessed. It has been shown that the proposed technique offers better accuracy in determining the Miller capacitors, especially $C_{GD}$ of the device relative to other reported analytical capacitor models. This improved accuracy has been achieved by involving the entire Schottky barrier depletion layer piecewise for the assessment of charges defining the Miller capacitors. Thus, the developed technique could be a useful tool in assessing the AC response of the device with more precision.
Highlights
Silicon carbide (SiC) field-effect transistors (FETs) are potential candidates for high-temperature and highfrequency applications, because they offer higher breakdown voltage and higher carrier mobility [1]
We have extended the work of Murray et al in which they have calculated analytical expressions for CGS and CGS ) and gate-to-drain ( (CGD) by taking into account only three regions underneath the Schottky barrier gate
To check the accuracy of the proposed Region-IV Miller capacitors model in contrast to other models, Figures 4 and 5 have been plotted, where experimental data of a submicron SiC metal–semiconductor field-effect transistors (MESFETs) is compared for CGD and CGS capacitors, respectively
Summary
Silicon carbide (SiC) field-effect transistors (FETs) are potential candidates for high-temperature and highfrequency applications, because they offer higher breakdown voltage and higher carrier mobility [1]. Statz et al [5] showed that at zero or reverse bias, there is a large capacitance present between source and gate of the device that could cause large error if not taken into account Considering this concept, they calculated total charge under the gate and derived expressions for CGS and CGD. We have extended the work of Murray et al in which they have calculated analytical expressions for CGS and CGD by taking into account only three regions underneath the Schottky barrier gate In their calculation, they ignored the extension of the depletion towards the drain side of the gate, which could have a significant contribution in charge accumulation, especially in submicron devices.
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