Abstract
Since hotspots and temperature gradients are reliability and performance-critical issues in processors, thermal awareness finds a vital place in the processor design cycle. Incorporating thermal awareness at the level of physical design, this work proposes a new, fast, and efficient thermal aware placement algorithm called the Thermal Aware Matrix Placement Optimizer (TAMPO) for gate arrays. The algorithm TAMPO is composed of the following components: an improved heat diffusion aware cell arrangement technique called the Initial Matrix Generator (IMaGe), a unique stochastic thermal model based on a thermally improved interpretation of the well known Matrix Synthesis Problem (MSP) and a Simulated Annealing (SA) engine for finding the global optimum solution. TAMPO targets to reduce the peak temperature while maintaining improved values of temperature gradients and the standard deviation in cell temperature with respect to the average chip temperature. This work also presents a methodology, the Co-optimized TAMPO, which extends the concept of TAMPO to simultaneously optimize the thermal attributes and the wirelength of a chip. The proposed algorithms realize a placement in matrix arrangement and upon experimentation on the ISCAS89 benchmark circuits encouraging results have been obtained.
Highlights
Thermal management has always been a challenge in VLSI design, since processors containing billions of transistors and pulsating at gigahertz frequencies, generate a huge amount of heat in small areas and often suffer from hotspots and high temperature gradients
A power model is required to estimate the power of the clusters generated by the Gate Array Packer (GAP) algorithm
We have generated the power of the rectangular cells according to [27] varying randomly between 4.06 x106 W/m2 to 0.22 x 106 W/m2 for 90 nm processor to test the effectiveness of the placement algorithms
Summary
Thermal management has always been a challenge in VLSI design, since processors containing billions of transistors and pulsating at gigahertz frequencies, generate a huge amount of heat in small areas and often suffer from hotspots and high temperature gradients. Hotspot tool takes considerable time overhead in solving the temperature value from the compact thermal model In this regards the MSP placement methodology proposed in [5] smartly avoids the expensive computation of actual temperature estimation during the optimization process and provides a fast solution to the thermal aware placement problem of gate array ICs. according to [9] and [10] the temperature of a functional block is influenced by the length of its shared boundary as well as the power density differences with the neighboring blocks. The die boundary wall has an adiabatic influence on the internally generated heat and the temperature of a functional block is characterized by its relative position from the die boundary wall These thermal considerations have been ignored by the works done till on MSP [5], [11] - [14] for the thermal aware placement. The IMaGe generates square matrix and minimum-cell matrix placements. 3) It presents an improved thermal model, designed by modifying the thermal metric of the MSP viz. local summative heat of a submatrix region or thermal zone along with its reflective heat component from the adiabatic die boundary wall. 4) It presents the placement algorithm, Thermal Aware Matrix Placement Optimizer (TAMPO) which incorporates the IMaGe, the proposed thermal model, and a Simulated Annealing (SA) engine to give a fast optimization in peak temperature, temperature gradient, and the standard deviation in temperature of cells in matrix placement. 5) It further extends the concept of TAMPO to generate a placement strategy called the Co-optimized TAMPO which optimizes the thermal attributes and the wirelength simultaneously. 6) it reconstructs few reference placement algorithms; one based on the Hotspot tool [6], [7], [28], one based on the Simple Approximation algorithm [5], and the other based on the thermal aware placement algorithm [11] to validate the performance of the proposed placement algorithms
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