Abstract
3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, however, not precise enough for the development of state-of-the-art 3D NAND. In this circumstance, an accurate measurement of dimension for as-formed staircase patterns is of great importance and technical interest. In this paper, an improved measurement method is proposed to meet the requirement for higher precision. By taking the overlay into account, a calculation formula for measuring the dimensional error of as-formed staircase is derived for the first time. Two kinds of anchor design (convex SS0 and concave SS0) are put forward to perform dedicated experiments. Achieved results show that the measurement error of as-formed staircase using this improved method is improved from 31.6 nm for normal measurement method to 14.1 nm. The dimensional uniformity of as-formed staircase is therefore improved significantly which in turn leads to well controlled word line leakage. Furthermore, in advanced staircase structure of stair divided scheme (SDS), the convex SS0 shows an advantage in cost compared to the concave SS0.
Highlights
The 3D NAND has become a mainstream technology in flash memory [1]–[6]
BEST LITHOGRAPHY CONDITION FOR STAIRCASE Fig. (5) shows that the distance between SS1 and SS0 increases with the exposure energy during lithography in 39 layers of staircase
The best lithography conditions of staircase in other layers are all obtained in this way as SS1
Summary
The 3D NAND has become a mainstream technology in flash memory [1]–[6]. with the increase of the stack numbers, more and more challenges have been arising in the manufacturing of 3D NAND, such as the control of multilayer thickness [7], precision and cost for forming staircase patterns [8]–[11], etch of channel hole with ultra-high aspect ratio [12]–[15], stress engineering [16]–[18], and defect detection [19] etc. It is easy to measure each stair while it is challenging to measure the dimension of protection patterns for staircase in nanometer size precisely. In order to meet the requirement for higher precision as the stack number of 3D NAND increases, an improved measurement method for the dimension of the staircase pattern is proposed. 2(a) and 2(b) display the dimension measurement method of large patterns proposed by Huang et al As shown in Fig. 2 (a), a reference mark is set around the periphery of the staircase protection pattern, and the distance from the edges of staircase patterns to the reference mark edges is measured. The boundaries of the staircase patterns are defined In this scheme, the error in width of the reference mark can cause the measurement error, which further leads to the error in the dimension of staircase. The dimension of staircase protection patterns is obtained using the distances from the left and right edges of the staircase protection patterns to the center of two anchors on each side
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