An improved delayed signal cancellation PLL for fast grid synchronization under distorted and unbalanced grid condition

Abstract

Phase locked loop (PLL) technique is widely used in grid synchronization applications. The phase estimation accuracy and dynamic response speed of the conventional PI based synchronous reference frame PLL (SRF-PLL) compromise when grid voltage is distorted and/or unbalanced. To overcome this challenge, Delayed Signal Cancellation based PLL (DSC-PLL) was proposed recently. In this paper, an improved DSC-PLL that incorporates a moving average filter and a second-order phase lead compensator is suggested. This PLL features high filtering capability and fast dynamic response since it can eliminate all even and odd harmonics with a simple structure while maintaining high bandwidth. The small signal model of the improved PLL is analyzed and parameters design procedure is discussed. Simulation results are presented to validate the effectiveness of the proposed method.