An Improved Capsule Network (WaferCaps) for Wafer Bin Map Classification Based on DCGAN Data Upsampling

Abd Al Rahman M Abu Ebayyeh,Alireza Mousavi,Sebelan Danishvar

doi:10.1109/tsm.2021.3134625

Abd Al Rahman M Abu Ebayyeh, Alireza Mousavi + Show 1 more

Open Access

https://doi.org/10.1109/tsm.2021.3134625

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Abstract

Wafer bin maps contain vital information that helps semiconductor manufacturers to identify the root causes and defect pattern failures in wafers. Conventional manual inspection techniques in inspecting these failures are labour intensive and cause prolonged production cycle time. Therefore, automatic inspection techniques can solve this problem. This paper proposes a deep learning approach based on deep convolutional generative adversarial network (DCGAN) and a new Capsule Network (WaferCaps). DCGAN was used to upsample the original dataset and therefore increase the data used for training and balance the classes at the same time. While WaferCaps was proposed to classify the defect patterns according to eight classes. The performance of our proposed DCGAN and WaferCaps was compared with different deep learning models such as the original Capsule Network (CapsNet), CNN, and MLP. In all of our experiment, WM-811K dataset was used for the data upsampling and training. The proposed approach has shown an effective performance in generating new synthetic data and classify them with training accuracy of 99.59%, validation accuracy of 97.53% and test accuracy of 91.4%.

Highlights

A DVANCES in semiconductor technology and design have been the driving forces behind the successful progress of microelectronic and optoelectronic devices
We considered the original and mixed datasets for this comparison to investigate the effect of using the synthetic wafer bin map (WBM) generated by Deep Convolutional Generative Adversarial Network (DCGAN) on the test accuracy of our proposed WaferCaps
We demonstrated the efficiency of using DCGAN for all the defect pattern in Sections III-A and IV-A

Summary

Introduction

A DVANCES in semiconductor technology and design have been the driving forces behind the successful progress of microelectronic and optoelectronic devices. The fabrication process for the semiconductor wafers is complex and consist of many stages that should take place in a clean room environment, such as oxidation, photolithography, etching, ion implementation, and metallization, which requires monitoring many key process parameters. The complexity of these steps makes the wafer prone to many kinds of defects and failures; wafer testing is an essential step in order to provide necessary information on specific manufacturing problems, which can reduce products’ flaws and lead to early prevention [3].

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