An improved attack on clock-controlled shift registers based on hardware implementation

Abstract

We cryptanalyze a type of stream generator with three linear-feedback shift registers that are mutually clocked in a stop/go manner and have the property of sequences of state space convergence. By guessing the clock-controlled sequence and employing a backtracking search, we propose an algorithm attack on the type of stream generator based on hardware implementation. In particular, the time complexity of the algorithm attacking the encryption algorithm A5/1 is 243.869 clock periods. With our hardware architecture, we investigate the implementation of the algorithm on field programmable gate array and application-specific integrated circuit for an attack on A5/1. As a result, we can retrieve the initial states of A5/1’s registers in 2 s on average without pre-computation if we have 64 known key-stream bits.