An improved architecture for designing modulo (2<i><sup>n</sup></i>-2<i><sup>p</sup></i>+1) multipliers

Abstract

In this express, we have proposed an improved architecture for designing efficient modulo (2n-2p+1) multipliers on the condition n≥2p. The proposed modulo (2n-2p+1) multipliers can improve the current state of the art by 7.7-42.5% in terms of area and 13.1-44.2% in terms of performance delay on the average or by 60.5% in terms of area with the equivalent delay performance.