An Improved Analytical Model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET

Abstract

Recent studies have pointed out that FinFET are immune to short channel effects (SCEs) but their performances at high frequencies are compromised due to strong fringing field between gate and source/drain region. Because of technological advancement, the gate structure of MOSFET has been improved from planar to nonplanar with an enhancement in the number of controlling gates. In this paper we propose FinFET structure for high frequency applications. The proposed model has been verified with finite element numerical simulations as well as with reported experimental measurements. In this paper, we propose for the first time an analytical model of Outer Fringe Capacitance of Multifin Diamond Shaped Raised Source/Drain FinFET. The development of parasitic model is necessary for accurate quantitative prediction of the parasitics introduced by each part of the device structure. The relative contribution of the total parasitic capacitance is addressed as well as their impact on RF-figure of merit (RF-FOM) (cut-off frequency fT) is presented. This work presents the possibility to improve fT by about 42% due to reduced parasitic gate capacitance that results from faceted surfaces of S/D region.