An implicit acceleration algorithm in test generation for VLSI circuits

Abstract

A fast test generation algorithm called FPODEM (Fast PODEM) is developed to improve the original PODEM algorithm. FPODEM can generate test patterns more quickly to detect all single-stuck faults (including fanout faults) in combinational circuits. In order to accelerate the algorithm of test generation it is necessary to reduce the total number of PI (primary input) assignments which are examined to generate and propagate the D-cubes for all single-stuck faults. The idea of backtracking in combination with the input-sequence-reordering technique is developed to increase the speed of test pattern generation. No self-masking problem needs to be considered in this algorithm, i.e. all detectable faults can be detected. It is shown that the FPODEM algorithm is faster and more efficient than the PODEM algorithm. The algorithm and data structure used in FPODEM are described. The results of simulation on combinational circuits demonstrate that FPODEM performs test generation quickly and efficiently, especially when the size of the circuit under test is increased. >