An implementation of random single input change technique for low-power test

Abstract

This paper presents a low-power test scheme by using random single input change (RSIC) technique. By adding simple control logic on original linear feedback shift register (LFSR), the output of LFSR is modified, and RSIC test sequence can be generated. The new RSIC sequence optimizes the switching activity of circuit-under-test (CUT), and then result in decrease of test power consumption. Initially, the theoretical bases of the generation of RSIC test sequences are introduced. Then a test implementation for CC4028 integrated circuits is analyzed. The result show that Single Input Change test sequence are more effective than classical Multiple Input Change test sequence when a power test is targeted, 50% of the switching activity is reduced and has no impact on the fault coverage.