An Implementation of Montgomery Modular Multiplier Based on KO-3 Multiplication

Abstract

In the public-key cryptographic algorithms like RSA and ECC algorithms, the modular multiplier is the basic and frequently used operation. The core of the modular multiplier is the large integer multiplication. In this paper, we firstly propose a design of multicycle 258-bit KO-3 multiplication based on deduced Karatsuba-Ofman algorithm and further apply this multiplication in the 256-bit pipeline Montgomery modular multiplier. The design is implemented with Verilog hardware description language and we get the synthesis report with Synopsys Design Compiler under SMIC 65nm library. Our design runs a Montgomery modular multiplier in 17 clock cycles and the total latency is 37.4ns. The area of the design is 145281 um2 approximately. Compared with other designs under the same library, our design costs less area and power and can balance the delay-area at the same time.