An ILP-based DMA Data Transmission Optimization Algorithm for MPSoC

Abstract

With the rapid development of integrated circuit design technology and the processed tasks and data volumes growing, MPSoC is becoming increasingly popular in a variety of applications. In MPSoC design, parallelism is a very important issue, for example, how to realize task parallelism and data parallelism. Focusing on this issue, this paper analyzes the role of DMA and presents an ILP-Based DMA data transmission optimization algorithm to reduce the pipeline time when employing multi-stage pipeline scheduling method to solve task parallelism and data parallelism. The proposed ILP model integrates task allocation/schedule and data transmission and thus realizes the optimal parallelism of data transmission and data processing. In addition, we divide data transmission of ILP model into four cases: (1) DMA0, do not use DMA to optimize data transmission; (2) DMA1, use DMA to transmit data between SPM and off-chip memory; (3) DMA2, use DMA to transmit data between SPM and SPM, SPM and off-chip memory; (4) DMA3, use DMA to transmit and prefetch all data. Simulation results show that the ILP model with DMA3 can reduce the pipeline time 17.8% compared with that of the ILP model with DMA0.