An hierarchical VLSI neural network architecture

Abstract

As neural network systems are scaled up in size it will become extremely difficult, if not impossible, to maintain full connectivity. A digital architecture which exhibits hierarchical connectivity similar to that observed in many biological neural networks is described. At the lowest level, clusters of fully connected neurons correspond to subnetworks. These subnetworks are then sparsely connected to form the complete neural network system. The architecture exploits the inherent density and large bandwidth of on-chip RAM and can use either a large number of bit-serial processors or a reduced number of bit-parallel processors. A prototype chip which implements a complete subnetwork has been fabricated in 3- mu m CMOS and is fully functional. >