An FPGA/MPSoC Based Low Latency Onboard SAR Processor

Abstract

This paper describes the concept and prototype implementation of a low latency spaceborne onboard Synthetic Aperture Radar (SAR) processor runing on a Multi-Processor-System-On-Chip (MPSoC) computing device combining an ARM processor and a Field-Programmable-Gate-Array (FPGA). The SAR processor is designed to generate SAR imagery from TerraSAR-X stripmap data for subsequent ship detection and sea state determination. Low latency data processing is a key development goal. Currently, a raw data block of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\mathrm{k}\times 32\mathrm{k}$</tex> samples, covering 375 km <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to 500 km <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , is focused on the hardware within 4 s. Together with an attached level-2 ship detection, wind, and sea state processor, running on the same device, a SAR data processing chain for generation of maritime alerts is formed. This chain is part of a larger prototype system being developed in the frame of the H2020 EO-ALERT project which further comprises an optical data chain, data compression/encryption, and scheduling on multiple reconfigurable MPSoC boards.