Abstract
Direct digital synthesizers (DDS), or numerically controlled oscillators (NCO), are important components in many digital communication systems, such as digital radios and modems, software-defined radios, digital down/up converters for cellular and PCS base stations, etc. A common method for digitally generating a complex or real valued sinusoid employs a lookup table scheme. This paper presents a FPGA-based method which can significantly reduce the Spurious Free Dynamic Range (SFDR). The proposed design is implemented on Xilinx Virtex 5 FPGA and the simulation results are compared with previous results to demonstrate significant improvement in reducing SFDR.
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