An FPGA-based MVDR Beamformer Using Dichotomous Coordinate Descent Iterations

Abstract

The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD core. Antenna beampatterns obtained from weights calculated in the fixed-point FPGA platform are compared with those of a floating-point simulation. The comparison shows good match of the results for linear arrays of as large as 64 elements. For a 64-element array, the proposed design could provide a weight update rate as high as 28 kHz.