Abstract
Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2 (3, 6)-regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10-6 at 2 dB over AWGN channel while performing maximum 18 decoding iterations.
Highlights
In the past few years, the recently rediscovered low-density parity-check (LDPC) codes [1, 2, 3] have received a lot of attention and have been widely considered as next-generation error-correcting codes for telecommunication and magnetic storage
In this paper, applying the joint code and decoder design methodology, we develop an elaborate (3, k)-regular LDPC code high-speed partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2 (3, 6)-regular LDPC code decoder using Xilinx Virtex FPGA (Field Programmable Gate Array) device
(2) Develop a partly parallel decoder that is configured by a set of constrained random parameters and defines a (3, k)-regular LDPC code ensemble, in which each code is a subcode of C2 and has the parity-check matrix H = [HT, HT3 ]T
Summary
In the past few years, the recently rediscovered low-density parity-check (LDPC) codes [1, 2, 3] have received a lot of attention and have been widely considered as next-generation error-correcting codes for telecommunication and magnetic storage. For any given LDPC code, due to the randomness of its Tanner graph, it is nearly impossible to directly develop a high-speed partly parallel decoder architecture. In this paper, applying the joint code and decoder design methodology, we develop an elaborate (3, k)-regular LDPC code high-speed partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2 (3, 6)-regular LDPC code decoder using Xilinx Virtex FPGA (Field Programmable Gate Array) device. To achieve good error-correcting capability, the LDPC code decoder architecture has to possess randomness to some extent, which makes the FPGA implementations more challenging since FPGA has fixed and regular hardware resources.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
