An FPGA implementation of AES with support for counter and feedback modes

Abstract

The advanced encryption standard (AES) is a symmetric key block cipher that has been approved by NIST as a replacement for the data encryption standard (DES). In this paper, we present an FPGA implementation for AES. Unlike most of the common implementations that support only ECB mode, our design supports five modes of operation. In particular, it supports ECB, CBC, CFB, OFB and CTR modes. The design occupies 7452 slices of a Xilinx Virtex-II Pro XC2VP50, features a maximum clock speed of 56.3MHz and produces throughput up to 480.427 Mbps, 423.906 Mbps and 379.284 Mbps for 128, 192 and 256-bit keys respectively. A simple level of key agility is also supported. A physical hardware prototype of the design is employed as a further demonstration of the design's functional abilities.