Abstract

In this paper, we present an alternative and improved FPGA hardware implementation for a phylogenetic tree reconstruction with maximum parsimony algorithm. As in our previous work, the approach is based on a particular stochastic local search algorithm that uses the Indirect Calculation of Tree Lengths method. However, now we use an alternative second-pass optimization method, for the first time, and modify the rearrangement evaluation process. As a result, we reduce the execution time by half for these two steps in the algorithm. We compare execution times against our previous hardware approach for six real-world biological datasets, obtaining an acceleration rate of around 1.2 times faster. We also show a comparison against the phylogenetic software TNT.

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