An FPGA Emulation Platform for Polar Codes

Abstract

While polar codes are a promising candidate of error correcting codes for both fiber optical communication and data storage applications, it is very time consuming, or even infeasible, to evaluate the bit error rate (BER) performance of polar codes with the software Monte-Carlo simulation, since these applications have a stringent requirement for the BER as low as 10-12 to 10-15. In this paper, we propose an FPGA emulation platform to tackle this problem. Several features are added to improve the adaptability of our emulation platform, and these features also set our FPGA emulation platform apart from prior FPGA implementations for polar codes. First, our platform consists of the encoder, the channel model, and the decoder, and it supports two channel models: the additive white Gaussian noise (AWGN) channel and the binary symmetric channel (BSC). Furthermore, an embedded CPU and an AXI interface are integrated so that our platform can be reconfigured to test different codes without re-implementing the decoder. Finally, our decoder has a multi-mode feature, which not only provides a way to test the error performance of both successive cancelation algorithm and successive cancelation list algorithm with different list sizes, but also provides various tradeoffs between throughput and error performance.